Enabling business’s first 64Gbps UCIe IP following profitable launch of Alphawave Semi’s 36Gbps UCIe Gen2 IP on TSMC’s 3nm know-how, supporting each customary substrate packaging high-yield, low-cost natural (NYSE:) and superior packaging applied sciences.
LONDON & TORONTO–(BUSINESS WIRE)–Alphawave Semi (LSE: AWE), a worldwide chief in high-speed connectivity and compute silicon for world know-how infrastructure, is proud to introduce the primary Common Chiplet Interconnect Specific ( UCIe™) 64 Gbps business customary. ) Die-to-Die (D2D) IP subsystem to ship unprecedented chipset interconnect knowledge charges, setting a brand new customary for ultra-high efficiency D2D connectivity options within the business. The third-generation 64Gbps IP subsystem builds on the successes of the most recent silicon-proven Gen2 36Gbps IP subsystem and 24Gbps Gen1 and is obtainable in TSMC’s 3nm know-how for normal and superior packaging. Confirmed silicon success and bandout milestones pave the best way for Alphawave Semi’s Gen3 UCIe™ IP subsystem providing.
Alphawave Semi is about to revolutionize connectivity with its 64Gbps UCIe Gen3 IP, delivering over 20Tbps/mm bandwidth density, with ultra-low energy consumption and latency. This resolution is very configurable and helps a number of protocols, together with AXI-4, AXI-S, CXS, CHI and CHI-C2C, to satisfy the rising calls for for high-performance connectivity on disaggregated techniques in high-performance computing (HPC) , knowledge facilities, and synthetic intelligence (AI) purposes.
The design conforms to the most recent UCIe™ specification and incorporates a scalable structure with superior testability options, together with stay well being monitoring per lane, making it a sturdy basis and enabling ecosystem of open and interoperable chipsets.
UCIe D2D interconnects facilitate a spread of ordinary and rising chipset connectivity situations. Frequent makes use of embrace linking compute chipsets for constant, low-latency connection through UCIe’s streaming capabilities, in addition to connecting compute to I/O chipsets utilizing UCIe interfaces with PCIe , CXL or Ethernet. Moreover, optical resynchronizers can leverage UCIe chip structure to determine dependable, low-latency optical I/O hyperlinks by optical engines, thereby bettering off-system connectivity. This helps the event of low-power, high-throughput options in knowledge facilities and AI/ML techniques.
For top-performance purposes, making a customized HBM core chip utilizing the most recent UCIe customary is a cutting-edge method that entails tight integration of reminiscence chips with compute chips to realize extraordinarily excessive bandwidth. excessive in addition to low latency between parts. This enables the die-to-die shoreline already occupied on the principle chip to be reused for core-to-core or core-to-I/O connections. This method considerably optimizes reminiscence transactions in AI purposes the place low energy and lowered latency are efficiency differentiators.
The UCIe Consortium is happy to see its members obtain essential milestones comparable to registrations, which reveal the rising adoption of the UCIe specification, mentioned Brian Rea, Chair of the UCIe Consortium Advertising and marketing Working Group. UCIe is the cornerstone of the chipset business, offering a sturdy resolution for high-speed, low-latency die-to-die interconnects. By adopting open requirements, we empower the business to speed up innovation, cut back time to market, and ship breakthrough applied sciences.
“Our profitable integration of 36Gbps UCIe™ Gen2 IP on 3nm know-how builds on our confirmed 3nm UCIe IP on silicon with CoWoS ® packaging,” mentioned Mohit Gupta, senior vice chairman and Managing Director, Customized Silicon & IP, Alphawave Semi. “This achievement paves the best way for our 64Gbps Gen3 UCIe IP, which is poised to ship high-performance and 20Tbps/mm throughput capabilities to our clients who want to maximise shoreline density for essential AI bandwidth wants in 2025.
This achievement, alongside Alphawave Semi’s first confirmed 3nm silicon Gen1 UCIe IP, reaffirms the corporate’s fast progress as a pacesetter in high-performance chip connectivity options with a complete suite of sub- Confirmed connectivity IP techniques on silicon, appropriate for hyperscalers and knowledge infrastructures. markets.
Be taught extra:
- Uncover the Alphawave Semi UCIe™ IP Options.
- Learn our current press launch on the business’s first silicon-proven 3nm UCIe™ IP.
- Discover our multiprotocol chiplet press launch.
- Watch the DAC 2024 video: From simulation to silicon: UCIe from Alphawave and Keysight™ Validation.
- Learn our weblog: Redefining XPU Reminiscence for AI Knowledge Facilities with a Customized HBM.
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About Alphawave Semi
Alphawave Semi is a worldwide chief in broadband connectivity and compute silicon for world know-how infrastructure. Confronted with the exponential development of information, Alphawave Semi’s know-how addresses a essential want: enabling knowledge to journey quicker, extra reliably and with greater efficiency at decrease consumption. We’re a vertically built-in semiconductor firm and our IP, customized silicon and connectivity merchandise are deployed by main world clients in knowledge middle, compute, networking, AI, 6G/5G, autonomous autos and storage. Based in 2017 by an skilled technical crew with a confirmed observe report in semiconductor mental property licensing, our mission is to speed up the essential knowledge infrastructure on the coronary heart of our digital world. To study extra about Alphawave Semi, go to: awavesemi.com.
Alphawave Semi and the Alphawave Semi emblem are emblems of Alphawave IP Group plc. All rights reserved.
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Claudia Cano-Manuel
Grand Bridges Advertising and marketing Restricted
press@awavesemi.com
+44 7562 182327
Supply: Alphawave Semi
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